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BS EN IEC 61188-6-1:2021

BS EN IEC 61188-6-1:2021

$167.15

Circuit boards and circuit board assemblies. Design and use – Land pattern design. Generic requirements for land pattern on circuit boards

Published By Publication Date Number of Pages
BSI 2021 36
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IEC 61188-6-1:2021 specifies the requirements for soldering surfaces on circuit boards. This includes lands and land pattern for surface mounted components and also solderable hole configurations for through-hole mounted components. These requirements are based on the solder joint requirements of the IEC 61191-1, IEC 61191-2, IEC 61191-3 and IEC 61191-4.

PDF Catalog

PDF Pages PDF Title
2 undefined
5 Annex ZA(normative)Normative references to international publicationswith their corresponding European publications
7 English
CONTENTS
9 FOREWORD
11 INTRODUCTION
12 1 Scope
2 Normative references
3 Terms and definitions
15 4 Design requirements
4.1 General
4.2 Product classification
16 4.3 General surface mount land and land pattern requirements
4.4 Component packages and soldering process
4.5 Soldering surface requirements
4.5.1 Main soldering techniques
4.5.2 Reflow soldering
17 4.5.3 Reflow soldering of leaded components
4.5.4 Wave soldering of surface mounted components
Figures
Figure 1 – Component placed on solder paste
18 Figure 2 – Component glued for wave soldering
19 4.5.5 Wave soldering of through-hole mounted components
Figure 3 – Wave soldered component with solder thieves
20 4.6 Soldering surface definition techniques
4.6.1 General
4.6.2 Metal defined lands
4.6.3 Solder mask defined lands
Figure 4 – Solder joint of a leaded component
21 4.6.4 Comparison of solder mask defined and non solder mask defined solderable surfaces
5 Component classification
5.1 General
5.2 Leaded components
22 5.3 Surface mount components
6 The proportional dimensioning system
Figure 5 – Leaded component – Capacitor
Figure 6 – Surface mount component – Chip capacitor
23 7 Terminal classification
7.1 Leaded terminals
7.2 Surface mount terminals
7.2.1 Terminal classes
7.2.2 Flat bottom terminals
Figure 7 – Flat bottom terminals with wettable flanks
24 7.2.3 General land requirements for flat bottom terminals
7.2.4 Flat bottom and vertical side terminals
Tables
Table 1 – Flat bottom terminals
Table 2 – Flat bottom/vertical side terminals
25 7.2.5 General land requirements for flat bottom and vertical side terminals
8 Requirements for lands of solder joints
8.1 Land/Pad dimensioning considerations of leaded terminals
8.2 Land dimensioning considerations of surface mount terminals
26 Annex A(informative)Dimensioning concept of former IEC 61188-5-1
A.1 Dimensioning systems
A.1.1 General
Figure A.1 – Profile tolerancing method
27 A.1.2 Component tolerancing
Figure A.2 – Example of 3216M capacitor dimensioning for optimum solder fillet condition
28 Figure A.3 – Profile dimensioning of gull-wing leaded SOIC
30 A.1.3 Solving for dimension Z
A.1.4 Land tolerancing
A.1.5 Fabrication allowances
31 A.1.6 Assembly tolerancing
Table A.1 – Conductor width tolerances
Table A.2 – Feature location accuracy
32 A.1.7 Dimension and tolerance analysis
33 Figure A.4 – Pitch for multiple leaded component
34 Annex B(informative)History of land dimensioning standards
B.1 IPC-782
B.2 IEC 61188-5 series
B.3 IPC-7351
35 Bibliography

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BS EN IEC 61188-6-1:2021
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