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BS EN IEC 63093-5:2018:2020 Edition

BS EN IEC 63093-5:2018:2020 Edition

$142.49

Ferrite cores. Guidelines on dimensions and the limits of surface irregularities – EP-cores and associated parts for use in inductors and transformers

Published By Publication Date Number of Pages
BSI 2020 24
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This part of IEC 63093 specifies the dimensions that are of importance for mechanical interchangeability for a preferred range of EP-cores made of ferrite, the essential dimensions of coil formers to be used with them and the locations of their terminal pins on a 2,50 mm printed wiring grid in relation to the base outlines of the cores and the effective parameter values to be used in calculations involving them. It also gives guidelines on allowable limits of surface irregularities applicable to EP-cores.

The specifications contained in this document are useful in negotiations between ferrite core manufacturers and users about surface irregularities.

The general considerations upon which the design of this range of cores is based are as given in Annex A.

PDF Catalog

PDF Pages PDF Title
2 undefined
5 Annex ZA(normative)Normative references to international publicationswith their corresponding European publications
7 CONTENTS
8 FOREWORD
10 1 Scope
2 Normative references
3 Terms and definitions
11 4 Primary dimensions
4.1 General
4.2 Dimensions of EP-cores
4.2.1 Principal dimensions
4.2.2 Effective parameter and Amin values
Figures
Figure 1 – Principal dimensions of EP-cores
Tables
Table 1 – Principal dimensions of EP-cores
12 4.3 Dimensional limits for coil formers
Figure 2 – Main dimensions of coil formers for EP-cores
Table 2 – Effective parameter and Amin values
Table 3 – Dimensional limits for coil formers for EP-cores
13 4.4 Pin locations and base outlines
Figure 3 – Pin locations (SMD type) viewed from the upper side of the board
14 5 Limits of surface irregularities
5.1 General
5.2 Examples of surface irregularities
Figure 4 – Pin locations (PTH type) viewed from the underside of the board
15 5.3 Chips and ragged edges
5.3.1 General
5.3.2 Chips and ragged edges on the mating surfaces
5.3.3 Chips and ragged edges on the other surfaces
Figure 5 – Examples of surface irregularities
16 Figure 6 – Chip location for EP-cores
17 Table 4 – Area and length reference for visual inspection
18 5.4 Cracks
5.5 Flash
5.6 Pull-outs
Figure 7 – Crack and pull-out locations for EP-cores
19 5.7 Crystallites
Figure 8 – Crystallite location for EP-cores
Table 5 – Limits for cracks
20 5.8 Pores
Figure 9 – Pore location for EP-cores
21 Annex A (normative)EP-core design
A.1 General
A.2 Pin location and base outlines
22 Bibliography

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BS EN IEC 63093-5:2018
$142.49