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BSI PD IEC/TS 62878-2-1:2015

BSI PD IEC/TS 62878-2-1:2015

$167.15

Device embedded substrate – Guidelines. General description of technology

Published By Publication Date Number of Pages
BSI 2015 34
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This part of IEC 62878 describes the basics of device embedding substrate.

This part of IEC 62878 is applicable to device embedded substrates fabricated by use of organic base material, which include for example active or passive devices, discrete components formed in the fabrication process of electronic wiring board, and sheet formed components.

The IEC 62878 series neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as an M-type business model in IEC 62421.

PDF Catalog

PDF Pages PDF Title
4 English
CONTENTS
6 FOREWORD
8 INTRODUCTION
9 1 Scope
2 Normative references
3 Terms, definitions and abbreviations
3.1 Terms and definitions
3.2 Abbreviations
4 Technology of device embedded substrate
4.1 Basic structures
10 Figures
Figure 1 – Examples of device embedded substrate
11 4.2 Technology of device embedded substrate
Figure 2 – Completed device embedded substrate (pad connection)
Figure 3 – Completed device embedded substrate (via connection)
12 Figure 4 – Structure of a pad connection type substrate on a passive device embedded ceramics base
Figure 5 – Structure of a device embedded substrate usinga ceramic board as the base (via connection type)
13 Tables
Table 1 – Classification of device embedding
14 4.3 Structures of device embedded substrates and terms used in this specification
Table 2 – Formed embedded device into the substrate
15 5 Jisso mounting and interconnection
5.1 General
Table 3 – Embedded device structure and fabrication process
16 Table 4 – Jisso mounting and interconnection of device embedded substrate
17 5.2 Interconnections and structures of device embedded substrate
Figure 6 – Entire structure of device embedded substrate
18 Figure 7 – Base (typical structure)
Figure 8 – Base (cavity structure)
Figure 9 – Base (insulator)
Figure 10 – Base (Conductive carrier – metal plate)
19 5.3 Device embedding by conventional process
Figure 11 – Passive device embedded ceramic board used as a base
Figure 12 – Ceramic board used as base (ceramic)
Figure 13 – Wire bonding connection and embedding of active device bare die
20 Figure 14 – Soldering connection and embedding of active device
Figure 15 – Soldering connection of square type passive device
Figure 16 – Conductive resin connection and embedding of active device
21 5.4 Device embedding using vias
Figure 17 – Conductive resin connection and embedding of square type passive device
Figure 18 – Soldering connection into through hole and embedding of passive device
Figure 19 – Connection by copper plating after embedding of active device
22 Figure 20 – Connection by copper plating after embedding of square type passive device
Figure 21 – Conductive paste connection after embedding of active device package
Figure 22 – Conductive paste connection after embeddingof square type passive device chip
23 Figure 23 – Device embedded substrate for device embedding in multi-layers
Figure 24 – Embedding of devices over multiple layers
Figure 25 – Resin base substrate
24 6 Naming of each section
6.1 General
6.2 General definition of top and bottom surfaces
Figure 26 – Conductor and metal sheet/copper foil as base substrate
Figure 27 – Device embedded substrate using passive device embedded ceramic substrates as base substrate – Second type
25 Figure 28 – Definition of top and bottom surfaces
Figure 29 – Definition of top and bottom surfaces (mounting of a mother board)
26 6.3 Naming of layers and interconnection position
Figure 30 – Names of layers in pad connection
27 Figure 31 – Additional information concerning the interconnection position
Figure 32 – Names of layers in via connection [I]
28 Figure 33 – Names of layers in via connection [II]
Figure 34 – Names of layers in via connection [III]
29 6.4 Definitions of insulation layer thickness, conductor gap and connection distance between terminal and conductor
6.4.1 General
6.4.2 Insulation layer thickness, conductor gap and electrode/conductor gap in pad connection
Table 5 – Names of layers of device embedded board
30 6.4.3 Insulation layer thickness, conductor gap and electrode/conductor gap in a via connection
6.5 Additional information
6.5.1 Additional information for the insulation layer
Figure 35 – Definition of insulating layer thickness and conductor gap in pad connection
Figure 36 – Definition of electrode gap in via connection
31 6.5.2 Additional information for conductor gap and electrode/conductor gap
Figure 37 – Additional illustration of insulating layer thickness
Figure 38 – Additional illustration for conductor gap and electrode/connector gap
32 Bibliography

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BSI PD IEC/TS 62878-2-1:2015
$167.15