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IEEE IEC 61691 5 2004

IEEE IEC 61691 5 2004

$169.54

IEC 61691-5 Ed.1 (IEEE Std 1076.4(TM)-2000): Behavioural Languages – Part 5: Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification

Published By Publication Date Number of Pages
IEEE 2004 436
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New IEEE Standard – Active. IEC 61691-5: 2004 Dual-logo document. Will replace IEEE Std 1076.4-2000. The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Speci cation is de ned in this standard.This modeling speci cation de nes a methodology which promotes the development of highly accurate, ef cient simulation models for ASIC (Application-Speci c Integrated Circuit)components in VHDL.

PDF Catalog

PDF Pages PDF Title
4 CONTENTS
6 Foreword
10 IEEE Introduction
12 1. Overview
1.1 Scope
1.2 Purpose
1.3 Intent of this standard
1.4 Structure and terminology of this standard
13 1.5 Syntactic description
14 1.6 Semantic description
1.7 Front matter, examples, figures, notes, and annexes
2. References
15 3. Basic elements of the VITAL ASIC modeling specification
3.1 VITAL modeling levels and compliance
16 3.2 VITAL standard packages
3.3 VITAL specification for timing data insertion
18 4. The Level 0 specification
4.1 The VITAL_Level0 attribute
4.2 General usage rules
19 4.3 The Level 0 entity interface
28 4.4 The Level 0 architecture body
30 5. Backannotation
5.1 Backannotation methods
31 5.2 The VITAL SDF map
46 6. The Level 1 specification
6.1 The VITAL_Level1 attribute
6.2 The Level 1 architecture body
47 6.3 The Level 1 architecture declarative part
6.4 The Level 1 architecture statement part
57 7. Predefined primitives and tables
7.1 VITAL logic primitives
59 7.2 VitalResolve
7.3 VITAL table primitives
65 8. Timing constraints
8.1 Timing check procedures
70 8.2 Modeling negative timing constraints
81 9. Delay selection
9.1 VITAL delay types and subtypes
82 9.2 Transition dependent delay selection
9.3 Glitch handling
83 9.4 Path delay procedures
85 9.5 Delay selection in VITAL primitives
86 9.6 VitalExtendToFillDelay
87 10. The Level 1 Memory specification
10.1 The VITAL Level 1 Memory attribute
10.2 The VITAL Level 1 Memory architecture body
88 10.3 The VITAL Level 1 Memory architecture declarative part
10.4 The VITAL Level 1 Memory architecture statement part
98 11. VITAL Memory function specification
11.1 VITAL memory construction
101 11.2 VITAL memory table specification
110 11.3 VitalDeclareMemory
112 11.4 VitalMemoryTable
114 11.5 VitalMemoryCrossPorts
116 11.6 VitalMemoryViolation
119 12. VITAL memory timing specification
12.1 VITAL memory timing types
120 12.2 Memory Output Retain timing behavior
121 12.3 VITAL Memory output retain timing specification
12.4 Transition dependent delay selection
122 12.5 VITAL memory path delay procedures
127 12.6 VITAL memory timing check procedures
132 13. The VITAL standard packages
13.1 VITAL_Timing package declaration
147 13.2 VITAL_Timing package body
174 13.3 VITAL_Primitives package declaration
243 13.4 VITAL_Primitives package body
313 13.5 VITAL_Memory package declaration
334 13.6 VITAL_Memory package body
423 Annex A (informative) Syntax summary
429 Annex B (informative) Glossary
431 Annex C (informative) Bibliography
432 Annex D (informative) List of Participants

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IEEE IEC 61691 5 2004
$169.54