{"id":371776,"date":"2024-10-20T02:26:17","date_gmt":"2024-10-20T02:26:17","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-iec-61188-6-12021\/"},"modified":"2024-10-26T04:14:23","modified_gmt":"2024-10-26T04:14:23","slug":"bs-en-iec-61188-6-12021","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-iec-61188-6-12021\/","title":{"rendered":"BS EN IEC 61188-6-1:2021"},"content":{"rendered":"

IEC 61188-6-1:2021 specifies the requirements for soldering surfaces on circuit boards. This includes lands and land pattern for surface mounted components and also solderable hole configurations for through-hole mounted components. These requirements are based on the solder joint requirements of the IEC 61191-1, IEC 61191-2, IEC 61191-3 and IEC 61191-4.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
2<\/td>\nundefined <\/td>\n<\/tr>\n
5<\/td>\nAnnex ZA(normative)Normative references to international publicationswith their corresponding European publications <\/td>\n<\/tr>\n
7<\/td>\nEnglish
CONTENTS <\/td>\n<\/tr>\n
9<\/td>\nFOREWORD <\/td>\n<\/tr>\n
11<\/td>\nINTRODUCTION <\/td>\n<\/tr>\n
12<\/td>\n1 Scope
2 Normative references
3 Terms and definitions <\/td>\n<\/tr>\n
15<\/td>\n4 Design requirements
4.1 General
4.2 Product classification <\/td>\n<\/tr>\n
16<\/td>\n4.3 General surface mount land and land pattern requirements
4.4 Component packages and soldering process
4.5 Soldering surface requirements
4.5.1 Main soldering techniques
4.5.2 Reflow soldering <\/td>\n<\/tr>\n
17<\/td>\n4.5.3 Reflow soldering of leaded components
4.5.4 Wave soldering of surface mounted components
Figures
Figure 1 \u2013 Component placed on solder paste <\/td>\n<\/tr>\n
18<\/td>\nFigure 2 \u2013 Component glued for wave soldering <\/td>\n<\/tr>\n
19<\/td>\n4.5.5 Wave soldering of through-hole mounted components
Figure 3 \u2013 Wave soldered component with solder thieves <\/td>\n<\/tr>\n
20<\/td>\n4.6 Soldering surface definition techniques
4.6.1 General
4.6.2 Metal defined lands
4.6.3 Solder mask defined lands
Figure 4 \u2013 Solder joint of a leaded component <\/td>\n<\/tr>\n
21<\/td>\n4.6.4 Comparison of solder mask defined and non solder mask defined solderable surfaces
5 Component classification
5.1 General
5.2 Leaded components <\/td>\n<\/tr>\n
22<\/td>\n5.3 Surface mount components
6 The proportional dimensioning system
Figure 5 \u2013 Leaded component \u2013 Capacitor
Figure 6 \u2013 Surface mount component \u2013 Chip capacitor <\/td>\n<\/tr>\n
23<\/td>\n7 Terminal classification
7.1 Leaded terminals
7.2 Surface mount terminals
7.2.1 Terminal classes
7.2.2 Flat bottom terminals
Figure 7 \u2013 Flat bottom terminals with wettable flanks <\/td>\n<\/tr>\n
24<\/td>\n7.2.3 General land requirements for flat bottom terminals
7.2.4 Flat bottom and vertical side terminals
Tables
Table 1 \u2013 Flat bottom terminals
Table 2 \u2013 Flat bottom\/vertical side terminals <\/td>\n<\/tr>\n
25<\/td>\n7.2.5 General land requirements for flat bottom and vertical side terminals
8 Requirements for lands of solder joints
8.1 Land\/Pad dimensioning considerations of leaded terminals
8.2 Land dimensioning considerations of surface mount terminals <\/td>\n<\/tr>\n
26<\/td>\nAnnex A(informative)Dimensioning concept of former IEC 61188-5-1
A.1 Dimensioning systems
A.1.1 General
Figure A.1 \u2013 Profile tolerancing method <\/td>\n<\/tr>\n
27<\/td>\nA.1.2 Component tolerancing
Figure A.2 \u2013 Example of 3216M capacitor dimensioning for optimum solder fillet condition <\/td>\n<\/tr>\n
28<\/td>\nFigure A.3 \u2013 Profile dimensioning of gull-wing leaded SOIC <\/td>\n<\/tr>\n
30<\/td>\nA.1.3 Solving for dimension Z
A.1.4 Land tolerancing
A.1.5 Fabrication allowances <\/td>\n<\/tr>\n
31<\/td>\nA.1.6 Assembly tolerancing
Table A.1 \u2013 Conductor width tolerances
Table A.2 \u2013 Feature location accuracy <\/td>\n<\/tr>\n
32<\/td>\nA.1.7 Dimension and tolerance analysis <\/td>\n<\/tr>\n
33<\/td>\nFigure A.4 \u2013 Pitch for multiple leaded component <\/td>\n<\/tr>\n
34<\/td>\nAnnex B(informative)History of land dimensioning standards
B.1 IPC-782
B.2 IEC 61188-5 series
B.3 IPC-7351 <\/td>\n<\/tr>\n
35<\/td>\nBibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Circuit boards and circuit board assemblies. Design and use – Land pattern design. Generic requirements for land pattern on circuit boards<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
BSI<\/b><\/a><\/td>\n2021<\/td>\n36<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":371786,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2641],"product_tag":[],"class_list":{"0":"post-371776","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-bsi","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/371776","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/371786"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=371776"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=371776"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=371776"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}