{"id":456996,"date":"2024-10-20T09:49:08","date_gmt":"2024-10-20T09:49:08","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1149-1-2013-9\/"},"modified":"2024-10-26T18:15:52","modified_gmt":"2024-10-26T18:15:52","slug":"ieee-1149-1-2013-9","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1149-1-2013-9\/","title":{"rendered":"IEEE 1149.1-2013"},"content":{"rendered":"

Revision Standard – Active. Circuitry that may be built into an integrated circuit to assist in the test, maintenance and support of assembled printed circuit boards and the test of internal circuits is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards. Also, a language is defined that allows rigorous structural description of the component-specific aspects of such testability features, and a second language is defined that allows rigorous procedural description of how the testability features may be used.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Std 1149.1-2013 Front Cover <\/td>\n<\/tr>\n
6<\/td>\nNotice to users
Laws and regulations
Copyrights
Updating of IEEE documents
Errata <\/td>\n<\/tr>\n
7<\/td>\nPatents <\/td>\n<\/tr>\n
8<\/td>\nParticipants <\/td>\n<\/tr>\n
10<\/td>\nIntroduction
History of the development of this standard <\/td>\n<\/tr>\n
11<\/td>\nChanges introduced by this revision <\/td>\n<\/tr>\n
14<\/td>\nContents <\/td>\n<\/tr>\n
19<\/td>\nFigures <\/td>\n<\/tr>\n
22<\/td>\nTables <\/td>\n<\/tr>\n
23<\/td>\nImportant Notice
1. Overview
1.1 Scope
1.2 Purpose
1.2.1 Overview of the operation of this standard <\/td>\n<\/tr>\n
24<\/td>\n1.2.2 Use of this standard to test an assembled product <\/td>\n<\/tr>\n
25<\/td>\n1.2.3 What is a boundary scan? <\/td>\n<\/tr>\n
26<\/td>\n1.2.4 Use of this standard to achieve other test goals <\/td>\n<\/tr>\n
27<\/td>\n1.3 Document outline
1.3.1 Specifications
1.3.2 Descriptions <\/td>\n<\/tr>\n
28<\/td>\n1.4 Text conventions
1.5 Logic diagram conventions <\/td>\n<\/tr>\n
29<\/td>\n2. Normative references <\/td>\n<\/tr>\n
30<\/td>\n3. Definitions, abbreviations, acronyms, and special terms
3.1 Definitions <\/td>\n<\/tr>\n
33<\/td>\n3.2 Abbreviations and acronyms <\/td>\n<\/tr>\n
34<\/td>\n3.3 Special terms <\/td>\n<\/tr>\n
35<\/td>\n4. Test access port (TAP)
4.1 Connections that form the TAP
4.1.1 Specifications
Rules
4.1.2 Description
4.2 Test clock input (TCK)
4.2.1 Specifications
Rules
Recommendations <\/td>\n<\/tr>\n
36<\/td>\nPermissions
4.2.2 Description
4.3 Test mode select (TMS) input
4.3.1 Specifications
Rules
Recommendations <\/td>\n<\/tr>\n
37<\/td>\n4.3.2 Description
4.4 Test data input (TDI)
4.4.1 Specifications
Rules
4.4.2 Description
4.5 Test data output (TDO) <\/td>\n<\/tr>\n
38<\/td>\n4.5.1 Specifications
Rules
4.5.2 Description
4.6 Test reset input (TRST*)
4.6.1 Specifications
Rules <\/td>\n<\/tr>\n
39<\/td>\nRecommendations
4.6.2 Description
4.7 Interconnection of components compatible with this standard
4.7.1 Specifications
Permissions
4.7.2 Description <\/td>\n<\/tr>\n
42<\/td>\n4.8 Subordination of this standard within a higher level test strategy
4.8.1 Specifications
Rules <\/td>\n<\/tr>\n
43<\/td>\nRecommendations
Permissions
4.8.2 Description <\/td>\n<\/tr>\n
44<\/td>\n5. Test logic architecture
5.1 Test logic design
5.1.1 Specifications
Rules
Permissions
5.1.2 Description <\/td>\n<\/tr>\n
45<\/td>\n5.2 Test logic realization
5.2.1 Specifications
Rules
5.2.2 Description <\/td>\n<\/tr>\n
46<\/td>\n6. Test logic controllers
6.1 TAP controller
6.1.1 TAP controller state diagram
6.1.1.1 Specifications
Rules <\/td>\n<\/tr>\n
47<\/td>\n6.1.1.2 Description
Test-Logic-Reset <\/td>\n<\/tr>\n
48<\/td>\nRun-Test\/Idle
Select-DR-Scan
Select-IR-Scan
Capture-DR <\/td>\n<\/tr>\n
49<\/td>\nShift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR <\/td>\n<\/tr>\n
50<\/td>\nCapture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR <\/td>\n<\/tr>\n
51<\/td>\nUpdate-IR
General <\/td>\n<\/tr>\n
52<\/td>\n6.1.2 TAP controller operation
6.1.2.1 Specifications
Rules <\/td>\n<\/tr>\n
55<\/td>\n6.1.2.2 Description <\/td>\n<\/tr>\n
60<\/td>\n6.1.3 TAP controller initialization
6.1.3.1 Specifications
Rules
6.1.3.2 Description <\/td>\n<\/tr>\n
61<\/td>\n6.2 Test mode persistence (TMP) controller
6.2.1 TMP controller state diagram
6.2.1.1 Specifications
Rules <\/td>\n<\/tr>\n
62<\/td>\nRecommendations
6.2.1.2 Description <\/td>\n<\/tr>\n
64<\/td>\n6.2.2 TMP controller operation
6.2.2.1 Specifications
Rules
Permissions
6.2.2.2 Description <\/td>\n<\/tr>\n
67<\/td>\n6.2.3 TMP controller initialization
6.2.3.1 Specifications
Rules
6.2.3.2 Description <\/td>\n<\/tr>\n
68<\/td>\n7. Instruction register
7.1 Design and construction of the instruction register
7.1.1 Specifications
Rules
Recommendations
Permissions
7.1.2 Description <\/td>\n<\/tr>\n
69<\/td>\n7.2 Instruction register operation
7.2.1 Specifications
Rules <\/td>\n<\/tr>\n
70<\/td>\n7.2.2 Description <\/td>\n<\/tr>\n
72<\/td>\n8. Instructions
8.1 Response of the test logic to instructions
8.1.1 Specifications
Rules
Recommendations
Permissions
8.1.2 Description <\/td>\n<\/tr>\n
73<\/td>\n8.2 Public instructions
8.2.1 Specifications
Rules
Recommendations <\/td>\n<\/tr>\n
74<\/td>\nPermissions
8.2.2 Description <\/td>\n<\/tr>\n
75<\/td>\n8.3 Private instructions
8.3.1 Specifications
Rules
Permissions
8.3.2 Description
8.4 BYPASS instruction
8.4.1 Specifications
Rules <\/td>\n<\/tr>\n
76<\/td>\nPermissions
Recommendations
8.4.2 Description
8.5 Boundary-scan register instructions
8.5.1 Overview of the operation of the boundary-scan register <\/td>\n<\/tr>\n
78<\/td>\n8.5.2 Specifications for boundary-scan register instructions <\/td>\n<\/tr>\n
79<\/td>\n8.6 SAMPLE instruction
8.6.1 Specifications
Rules
Recommendations
Permissions
8.6.2 Description <\/td>\n<\/tr>\n
80<\/td>\n8.7 PRELOAD instruction
8.7.1 Specifications
Rules <\/td>\n<\/tr>\n
81<\/td>\nRecommendations
Permissions
8.7.2 Description <\/td>\n<\/tr>\n
82<\/td>\n8.8 EXTEST instruction
8.8.1 Specifications
Rules <\/td>\n<\/tr>\n
83<\/td>\nRecommendations
Permissions
8.8.2 Description <\/td>\n<\/tr>\n
84<\/td>\n8.9 INTEST instruction <\/td>\n<\/tr>\n
85<\/td>\n8.9.1 Specifications
Rules
Recommendations
Permissions
8.9.2 Description <\/td>\n<\/tr>\n
88<\/td>\n8.10 RUNBIST instruction
8.10.1 Specifications
Rules <\/td>\n<\/tr>\n
89<\/td>\nRecommendations
Permissions
8.10.2 Description <\/td>\n<\/tr>\n
90<\/td>\n8.11 CLAMP instruction <\/td>\n<\/tr>\n
91<\/td>\n8.11.1 Specifications
Rules
Permissions
8.11.2 Description <\/td>\n<\/tr>\n
92<\/td>\n8.12 Device identification register instructions
8.13 IDCODE instruction
8.13.1 Specifications
Rules <\/td>\n<\/tr>\n
93<\/td>\nPermissions
8.13.2 Description
8.14 USERCODE instruction
8.14.1 Specifications <\/td>\n<\/tr>\n
94<\/td>\nRules
Permissions
8.14.2 Description <\/td>\n<\/tr>\n
95<\/td>\n8.15 ECIDCODE instruction
8.15.1 Specifications
Rules <\/td>\n<\/tr>\n
96<\/td>\nRecommendations
Permissions
8.15.2 Description
8.16 HIGHZ instruction
8.16.1 Specifications
Rules <\/td>\n<\/tr>\n
97<\/td>\nPermissions
8.16.2 Description <\/td>\n<\/tr>\n
98<\/td>\n8.17 Component initialization instructions and procedures
8.17.1 Specifications
Rules <\/td>\n<\/tr>\n
99<\/td>\nPermissions
Recommendations
8.17.2 Description <\/td>\n<\/tr>\n
103<\/td>\n8.18 INIT_SETUP and INIT_SETUP_CLAMP instructions
8.18.1 Specifications
Rules <\/td>\n<\/tr>\n
104<\/td>\nPermissions
8.18.2 Description
8.19 INIT_RUN instruction
8.19.1 Specifications
Rules <\/td>\n<\/tr>\n
105<\/td>\nRecommendations
Permissions
8.19.2 Description <\/td>\n<\/tr>\n
106<\/td>\n8.20 CLAMP_HOLD, CLAMP_RELEASE, and TMP_STATUS instructions
8.20.1 Specifications
Rules <\/td>\n<\/tr>\n
107<\/td>\nPermissions
8.20.2 Description <\/td>\n<\/tr>\n
110<\/td>\n8.21 IC_RESET instruction
8.21.1 Specifications
Rules <\/td>\n<\/tr>\n
111<\/td>\nRecommendations
Permissions
8.21.2 Description <\/td>\n<\/tr>\n
113<\/td>\n9. Test data registers
9.1 Provision of test data registers
9.1.1 Specifications
Rules <\/td>\n<\/tr>\n
114<\/td>\nPermissions
Recommendations
9.1.2 Description
Bypass register <\/td>\n<\/tr>\n
115<\/td>\nBoundary-scan register
9.1.2.1 Optional standard test data registers
Device identification register
Electronic chip identification register
Initialization data register
Initialization status register
TMP status register
Reset selection register
9.1.2.2 Design-specific test data registers <\/td>\n<\/tr>\n
116<\/td>\n9.2 Design and construction of test data registers
9.2.1 Specifications
Rules
Permissions
Recommendations <\/td>\n<\/tr>\n
117<\/td>\n9.2.2 Description <\/td>\n<\/tr>\n
118<\/td>\n9.2.3 TAP-to-TDR interface <\/td>\n<\/tr>\n
119<\/td>\n9.2.4 Test data register cell design examples <\/td>\n<\/tr>\n
120<\/td>\nGated-clock example TDR bit
Ungated-clock example TDR bits <\/td>\n<\/tr>\n
128<\/td>\n9.3 Operation of test data registers
9.3.1 Specifications
Rules
Permissions <\/td>\n<\/tr>\n
129<\/td>\nRecommendations
9.3.2 Description <\/td>\n<\/tr>\n
130<\/td>\n9.4 Design and control of test data register segments <\/td>\n<\/tr>\n
131<\/td>\n9.4.1 Specifications
Rules <\/td>\n<\/tr>\n
133<\/td>\nPermissions
Recommendations
9.4.2 Description
Excludable segments <\/td>\n<\/tr>\n
136<\/td>\nSelectable segments <\/td>\n<\/tr>\n
138<\/td>\n10. Bypass register
10.1 Design and operation of the bypass register
10.1.1 Specifications
Rules
10.1.2 Description <\/td>\n<\/tr>\n
140<\/td>\n11. Boundary-scan register
11.1 Introduction
11.1.1 Approach <\/td>\n<\/tr>\n
142<\/td>\n11.1.2 Signal paths to the on-chip system logic
11.1.3 Boundary-scan register cell <\/td>\n<\/tr>\n
144<\/td>\n11.2 Register design
11.2.1 Specifications
Rules <\/td>\n<\/tr>\n
145<\/td>\nPermissions <\/td>\n<\/tr>\n
146<\/td>\n11.2.2 Description
11.3 Register operation
11.3.1 Specifications
Rules <\/td>\n<\/tr>\n
147<\/td>\nPermissions <\/td>\n<\/tr>\n
148<\/td>\n11.3.2 Description
11.4 General rules regarding cell provision
11.4.1 Specification
Rules <\/td>\n<\/tr>\n
149<\/td>\nPermissions
11.4.2 Description <\/td>\n<\/tr>\n
153<\/td>\n11.5 Provision and operation of cells at system logic inputs
11.5.1 Specifications
Rules <\/td>\n<\/tr>\n
156<\/td>\nPermissions <\/td>\n<\/tr>\n
157<\/td>\n11.5.2 Description <\/td>\n<\/tr>\n
160<\/td>\n11.6 Provision and operation of cells at system logic outputs <\/td>\n<\/tr>\n
161<\/td>\n11.6.1 Specifications
Rules <\/td>\n<\/tr>\n
166<\/td>\nRecommendations
Permissions <\/td>\n<\/tr>\n
167<\/td>\n11.6.2 Description <\/td>\n<\/tr>\n
176<\/td>\n11.7 Provision and operation of cells at bidirectional system logic pins
11.7.1 Specifications
Rules
11.7.2 Description <\/td>\n<\/tr>\n
183<\/td>\n11.8 Redundant cells <\/td>\n<\/tr>\n
184<\/td>\n11.8.1 Specifications
Rules
Permissions
Recommendations
11.8.2 Description <\/td>\n<\/tr>\n
185<\/td>\n11.9 Special cases
11.9.1 Specifications
Permissions
11.9.2 Description <\/td>\n<\/tr>\n
188<\/td>\n12. Device identification register
12.1 Design and operation of the device identification register
12.1.1 Specifications
Rules
12.1.2 Description <\/td>\n<\/tr>\n
190<\/td>\n12.2 Manufacturer identity code
12.2.1 Specifications
Rules
Recommendations
12.2.2 Description <\/td>\n<\/tr>\n
191<\/td>\n12.3 Part-number code
12.3.1 Specifications
Rules
Recommendations
Permissions
12.3.2 Description <\/td>\n<\/tr>\n
192<\/td>\n12.4 Version code
12.4.1 Specifications
Rules
Recommendations
Permissions
12.4.2 Description <\/td>\n<\/tr>\n
193<\/td>\n13. Electronic chip identification (ECID) register
13.1 Design and operation of the ECID register
13.1.1 Specifications
Rules
Permissions
13.1.2 Description <\/td>\n<\/tr>\n
194<\/td>\n14. Initialization data register
14.1 Design and operation of the initialization data register
14.1.1 Specifications
Rules
Recommendations
Permissions <\/td>\n<\/tr>\n
195<\/td>\n14.1.2 Description <\/td>\n<\/tr>\n
197<\/td>\n15. Initialization status register
15.1 Design and operation of the initialization status register
15.1.1 Specifications
Rules
Recommendations
15.1.2 Description <\/td>\n<\/tr>\n
198<\/td>\n16. TMP status register
16.1 Design and operation of the TMP status register
16.1.1 Specifications
Rules
16.1.2 Description <\/td>\n<\/tr>\n
200<\/td>\n17. Reset selection register
17.1 Design and operation of the reset selection register <\/td>\n<\/tr>\n
201<\/td>\n17.1.1 Specifications
Rules
Permissions <\/td>\n<\/tr>\n
202<\/td>\n17.1.2 Description <\/td>\n<\/tr>\n
205<\/td>\n18. Conformance and documentation requirements
18.1 Claiming conformance to this standard
18.1.1 Specifications
Rules
Recommendations
Permissions
18.1.2 Description <\/td>\n<\/tr>\n
206<\/td>\n18.2 Prime and second source components
18.2.1 Specifications
Rules
18.2.2 Description
18.3 Documentation requirements
18.3.1 Specifications
Rules <\/td>\n<\/tr>\n
208<\/td>\n18.3.2 Description <\/td>\n<\/tr>\n
210<\/td>\nAnnex A (informative)
\nExample implementation using level-sensitive design techniques <\/td>\n<\/tr>\n
211<\/td>\nAnnex B (normative)
\nBoundary Scan Description Language (BSDL)
B.1 General information
B.1.1 Document outline
B.1.2 Conventions
B.1.3 BSDL history <\/td>\n<\/tr>\n
212<\/td>\nB.2 Purpose of BSDL
B.3 Scope of BSDL <\/td>\n<\/tr>\n
213<\/td>\nB.4 Relationship of BSDL to VHDL
B.4.1 Specifications <\/td>\n<\/tr>\n
214<\/td>\nRules
Permissions
B.5 Lexical elements of BSDL
B.5.1 Character set
B.5.1.1 Specifications
Rules <\/td>\n<\/tr>\n
215<\/td>\nB.5.2 BSDL reserved words
B.5.2.1 Specifications
Rules <\/td>\n<\/tr>\n
216<\/td>\nB.5.3 VHDL reserved and predefined words <\/td>\n<\/tr>\n
217<\/td>\nB.5.3.1 Specifications
Rules
B.5.4 Identifiers
B.5.4.1 Specifications
Rules <\/td>\n<\/tr>\n
218<\/td>\nB.5.5 Numeric literals
B.5.5.1 Specifications
Rules <\/td>\n<\/tr>\n
219<\/td>\nB.5.5.2 Description
B.5.6 Strings
B.5.6.1 Specifications
Rules <\/td>\n<\/tr>\n
220<\/td>\nB.5.6.2 Description
B.5.7 Information tag
B.5.7.1 Specifications
Rules
B.5.7.2 Description <\/td>\n<\/tr>\n
221<\/td>\nB.5.8 Comments
B.5.8.1 Specifications
Rules
B.6 Syntax definition
B.6.1 BNF conventions <\/td>\n<\/tr>\n
222<\/td>\nB.6.2 Commonly used syntactic elements
B.6.2.1 Specifications
Syntax <\/td>\n<\/tr>\n
223<\/td>\nRules <\/td>\n<\/tr>\n
224<\/td>\nB.7 Components of a BSDL description
B.7.1 Specifications
Rules <\/td>\n<\/tr>\n
225<\/td>\nPermissions
B.7.2 Description
B.8 Entity description
B.8.1 Overall syntax of the entity description
B.8.1.1 Specifications
Syntax <\/td>\n<\/tr>\n
226<\/td>\nRules
Recommendations
B.8.2 Generic parameter statement <\/td>\n<\/tr>\n
227<\/td>\nB.8.2.1 Specifications
Syntax
Rules
B.8.2.2 Description
B.8.2.3 Examples
B.8.3 Logical port description statement
B.8.3.1 Specifications
Syntax <\/td>\n<\/tr>\n
228<\/td>\nRules
Permissions
B.8.3.2 Description <\/td>\n<\/tr>\n
230<\/td>\nB.8.3.3 Example
B.8.4 Standard use statement <\/td>\n<\/tr>\n
231<\/td>\nB.8.4.1 Specifications
Syntax
Rules
B.8.4.2 Description <\/td>\n<\/tr>\n
232<\/td>\nB.8.4.3 Examples
B.8.4.4 Version control <\/td>\n<\/tr>\n
233<\/td>\nB.8.5 Use statement
B.8.5.1 Specifications
Syntax
Rules <\/td>\n<\/tr>\n
234<\/td>\nB.8.5.2 Description
B.8.5.3 Example
B.8.6 Component conformance statement
B.8.6.1 Specifications
Syntax <\/td>\n<\/tr>\n
235<\/td>\nRules
B.8.6.2 Description
B.8.6.3 Example
B.8.7 Device package pin mappings
B.8.7.1 Specifications
Syntax <\/td>\n<\/tr>\n
236<\/td>\nRules
Permissions
B.8.7.2 Examples <\/td>\n<\/tr>\n
237<\/td>\nB.8.7.3 Description <\/td>\n<\/tr>\n
238<\/td>\nB.8.8 Grouped port identification <\/td>\n<\/tr>\n
239<\/td>\nB.8.8.1 Specifications
Syntax
Rules <\/td>\n<\/tr>\n
240<\/td>\nB.8.8.2 Description
B.8.8.3 Examples <\/td>\n<\/tr>\n
241<\/td>\nB.8.9 Scan port identification
B.8.9.1 Specifications
Syntax
Rules <\/td>\n<\/tr>\n
242<\/td>\nB.8.9.2 Description
Examples
B.8.10 Compliance-enable description
B.8.10.1 Specifications
Syntax
Rules <\/td>\n<\/tr>\n
243<\/td>\nPermissions
B.8.10.2 Description
B.8.10.3 Examples
B.8.11 Instruction register description <\/td>\n<\/tr>\n
244<\/td>\nB.8.11.1 Specifications
Syntax
Rules <\/td>\n<\/tr>\n
245<\/td>\nB.8.11.2 Description <\/td>\n<\/tr>\n
246<\/td>\nB.8.11.3 Examples
B.8.12 Optional device register description <\/td>\n<\/tr>\n
247<\/td>\nB.8.12.1 Specifications
Syntax
Rules
Recommendations
Permissions
B.8.12.2 Description <\/td>\n<\/tr>\n
248<\/td>\nB.8.12.3 Examples <\/td>\n<\/tr>\n
249<\/td>\nB.8.13 Register access description
B.8.13.1 Specifications
Syntax
Rules <\/td>\n<\/tr>\n
250<\/td>\nB.8.13.2 Examples
B.8.13.3 Description <\/td>\n<\/tr>\n
251<\/td>\nB.8.14 Boundary-scan register description <\/td>\n<\/tr>\n
253<\/td>\nB.8.14.1 Specifications
Syntax <\/td>\n<\/tr>\n
254<\/td>\nRules <\/td>\n<\/tr>\n
257<\/td>\nPermissions
B.8.14.2 Examples
Example 1 <\/td>\n<\/tr>\n
258<\/td>\nExample 2 <\/td>\n<\/tr>\n
259<\/td>\nB.8.14.3 Description <\/td>\n<\/tr>\n
260<\/td>\nB.8.14.3.1 element
B.8.14.3.2 element
B.8.14.3.3 element <\/td>\n<\/tr>\n
262<\/td>\nB.8.14.3.4 element
B.8.14.3.5 element
B.8.14.3.6 element
B.8.14.3.7 element <\/td>\n<\/tr>\n
263<\/td>\nB.8.14.3.8 element <\/td>\n<\/tr>\n
267<\/td>\nB.8.15 RUNBIST description <\/td>\n<\/tr>\n
268<\/td>\nB.8.15.1 Specifications
Syntax
Rules <\/td>\n<\/tr>\n
269<\/td>\nB.8.15.2 Examples
B.8.16 INTEST description <\/td>\n<\/tr>\n
270<\/td>\nB.8.16.1 Specifications
Syntax
Rules
B.8.16.2 Examples <\/td>\n<\/tr>\n
271<\/td>\nB.8.17 System clock requirements attribute
B.8.17.1 Specifications
Syntax
Rules <\/td>\n<\/tr>\n
272<\/td>\nB.8.17.2 Description
B.8.17.3 Examples
B.8.18 Register mnemonics description
B.8.18.1 Specifications
Syntax <\/td>\n<\/tr>\n
273<\/td>\nRules
B.8.18.2 Description <\/td>\n<\/tr>\n
274<\/td>\nB.8.18.3 Examples
Example 1
Example 2 <\/td>\n<\/tr>\n
275<\/td>\nExample 3 <\/td>\n<\/tr>\n
276<\/td>\nB.8.19 Register fields description <\/td>\n<\/tr>\n
277<\/td>\nB.8.19.1 Specifications
Syntax <\/td>\n<\/tr>\n
278<\/td>\nRules
B.8.19.2 Description <\/td>\n<\/tr>\n
280<\/td>\nB.8.19.3 Examples <\/td>\n<\/tr>\n
283<\/td>\nB.8.20 Register field assignment description <\/td>\n<\/tr>\n
284<\/td>\nB.8.20.1 Specifications
Syntax
Rules <\/td>\n<\/tr>\n
286<\/td>\nRecommendations <\/td>\n<\/tr>\n
287<\/td>\nB.8.20.2 Description <\/td>\n<\/tr>\n
293<\/td>\nB.8.21 Register assembly description
B.8.21.1 Specifications
Syntax <\/td>\n<\/tr>\n
294<\/td>\nRules <\/td>\n<\/tr>\n
297<\/td>\nPermissions
Recommendations
B.8.21.2 Description <\/td>\n<\/tr>\n
300<\/td>\nExcludable register segments and domain control <\/td>\n<\/tr>\n
301<\/td>\nSelectable register segments <\/td>\n<\/tr>\n
303<\/td>\nB.8.21.3 Examples
Initialization REGISTER_ASSEMBLY example <\/td>\n<\/tr>\n
305<\/td>\nBoundary-scan example
Power-domain control example <\/td>\n<\/tr>\n
307<\/td>\nIEEE 1500 WSP Examples <\/td>\n<\/tr>\n
310<\/td>\nB.8.22 Register constraint description
B.8.22.1 Specifications
Syntax <\/td>\n<\/tr>\n
311<\/td>\nRules <\/td>\n<\/tr>\n
312<\/td>\nB.8.22.2 Description <\/td>\n<\/tr>\n
313<\/td>\nB.8.22.3 Examples
B.8.23 Register and power port association attributes
B.8.23.1 Specifications
Syntax <\/td>\n<\/tr>\n
314<\/td>\nRules <\/td>\n<\/tr>\n
315<\/td>\nB.8.23.2 Description <\/td>\n<\/tr>\n
316<\/td>\nB.8.23.3 Examples <\/td>\n<\/tr>\n
317<\/td>\nB.8.24 User extensions to BSDL
B.8.24.1 Specifications
Syntax
Rules <\/td>\n<\/tr>\n
318<\/td>\nPermissions
B.8.24.2 Description
B.8.24.3 Examples <\/td>\n<\/tr>\n
319<\/td>\nB.8.25 Design warning
B.8.25.1 Specifications
Syntax
B.8.25.2 Description
B.8.25.3 Examples <\/td>\n<\/tr>\n
320<\/td>\nB.9 Standard BSDL Package STD_1149_1_2013 <\/td>\n<\/tr>\n
324<\/td>\nB.10 User-supplied BSDL packages
B.10.1 Specifications
Syntax <\/td>\n<\/tr>\n
325<\/td>\nRules <\/td>\n<\/tr>\n
327<\/td>\nRecommendations <\/td>\n<\/tr>\n
328<\/td>\nB.10.2 Description <\/td>\n<\/tr>\n
329<\/td>\nB.10.3 Examples
User-supplied package for boundary-register cells <\/td>\n<\/tr>\n
330<\/td>\nUser-supplied package body for internal registers
B.11 BSDL example applications
B.11.1 Typical application of BSDL <\/td>\n<\/tr>\n
333<\/td>\nB.11.2 Boundary-scan register description
B.11.2.1 Multiple cells per pin <\/td>\n<\/tr>\n
335<\/td>\nB.11.2.2 Internal boundary register cells <\/td>\n<\/tr>\n
336<\/td>\nB.11.2.3 Merged cells <\/td>\n<\/tr>\n
337<\/td>\nB.12 1990 version of BSDL <\/td>\n<\/tr>\n
338<\/td>\nB.12.1 1990 Standard VHDL Package STD_1149_1_1990 <\/td>\n<\/tr>\n
341<\/td>\nB.12.2 Typical application of BSDL, 1990 version <\/td>\n<\/tr>\n
342<\/td>\nB.12.3 Obsolete syntax <\/td>\n<\/tr>\n
343<\/td>\nB.12.3.1 Syntax
B.12.4 Miscellaneous points on 1990 version
B.13 1994 version of BSDL
B.13.1 Standard VHDL Package STD_1149_1_1994 <\/td>\n<\/tr>\n
347<\/td>\nB.14 2001 version of BSDL
B.14.1 Standard VHDL Package STD_1149_1_2001 <\/td>\n<\/tr>\n
351<\/td>\nAnnex C (normative)
\nProcedural Description Language (PDL)
C.1 General information
C.1.1 Purpose <\/td>\n<\/tr>\n
352<\/td>\nC.1.2 Dependence on Tool Command Language (Tcl)
C.1.3 Dependence on Boundary Scan Description Language (BSDL)
C.2 PDL concepts and use model
C.2.1 Use model introduction <\/td>\n<\/tr>\n
354<\/td>\nC.2.2 PDL levels
C.2.2.1 Level-0 PDL <\/td>\n<\/tr>\n
355<\/td>\nC.2.2.2 Level-1 PDL
C.2.3 PDL procedures <\/td>\n<\/tr>\n
356<\/td>\nC.2.4 Read and write with capture-shift-update sequence
C.2.5 Register state definition <\/td>\n<\/tr>\n
358<\/td>\nC.2.6 Level-0 PDL commands <\/td>\n<\/tr>\n
361<\/td>\nC.2.7 Specification of names and values <\/td>\n<\/tr>\n
362<\/td>\nC.2.8 Retargeting <\/td>\n<\/tr>\n
363<\/td>\nC.2.9 Simple PDL Example
U3.PDL <\/td>\n<\/tr>\n
364<\/td>\nMEMB.PDL
Chip_A.PDL <\/td>\n<\/tr>\n
365<\/td>\nC.3 PDL Level 0 command reference
C.3.1 Understanding a PDL \u201cstring\u201d <\/td>\n<\/tr>\n
366<\/td>\nC.3.2 BNF conventions <\/td>\n<\/tr>\n
367<\/td>\nC.3.3 PDL lexical elements and common syntax
C.3.3.1 Lexical element specifications
General rules <\/td>\n<\/tr>\n
368<\/td>\nNumeric literal rules <\/td>\n<\/tr>\n
369<\/td>\nIdentifier rules
Text string rules
C.3.3.2 Substitutions <\/td>\n<\/tr>\n
370<\/td>\nRules <\/td>\n<\/tr>\n
371<\/td>\nC.3.3.3 Common syntax
Syntax
Rules
Description <\/td>\n<\/tr>\n
372<\/td>\nC.3.3.4 PDL reserved words
Rules
Recommendations
C.3.4 PDL File
Syntax
Rules <\/td>\n<\/tr>\n
373<\/td>\nPermissions
C.3.5 Procedure definition commands
C.3.5.1 iSource command
Syntax
Rules
Example
C.3.5.2 iPDLLevel command <\/td>\n<\/tr>\n
374<\/td>\nSyntax
Rules
Permissions
Example
C.3.5.3 iProcGroup command <\/td>\n<\/tr>\n
375<\/td>\nSyntax
Rules
Permissions
Example
C.3.5.4 iProc command <\/td>\n<\/tr>\n
376<\/td>\nSyntax
Rules <\/td>\n<\/tr>\n
377<\/td>\nPredefined procedure names <\/td>\n<\/tr>\n
378<\/td>\nC.3.6 Test setup commands
C.3.6.1 iPrefix command
Syntax <\/td>\n<\/tr>\n
379<\/td>\nRules
Examples
C.3.6.2 iSetInstruction command
Syntax
Rules <\/td>\n<\/tr>\n
380<\/td>\nExamples
C.3.6.3 iClock and iClockOverride commands
Syntax
Rules <\/td>\n<\/tr>\n
381<\/td>\nExamples <\/td>\n<\/tr>\n
382<\/td>\nC.3.7 Test execution commands
C.3.7.1 iRead and iWrite commands
Syntax
Rules <\/td>\n<\/tr>\n
383<\/td>\nExamples <\/td>\n<\/tr>\n
384<\/td>\nC.3.7.2 iApply command <\/td>\n<\/tr>\n
386<\/td>\nSyntax
Rules <\/td>\n<\/tr>\n
387<\/td>\nRecommendations
Examples <\/td>\n<\/tr>\n
388<\/td>\nC.3.7.3 iScan command
Syntax <\/td>\n<\/tr>\n
389<\/td>\nRules
Examples
C.3.8 Flow-control commands
C.3.8.1 iCall command <\/td>\n<\/tr>\n
390<\/td>\nSyntax
Rules
Examples <\/td>\n<\/tr>\n
391<\/td>\nC.3.8.2 iRunLoop command
Syntax <\/td>\n<\/tr>\n
392<\/td>\nRules
Recommendations
Examples <\/td>\n<\/tr>\n
393<\/td>\nC.3.8.3 iLoop and iUntil commands
Syntax
Rules <\/td>\n<\/tr>\n
394<\/td>\nExample A
Example B
C.3.8.4 ifTrue, ifFalse and ifEnd commands <\/td>\n<\/tr>\n
395<\/td>\nSyntax
Rules
Example A <\/td>\n<\/tr>\n
396<\/td>\nExample B
C.3.9 Optimization commands
C.3.9.1 iMerge command <\/td>\n<\/tr>\n
397<\/td>\nSyntax
Rules
Example <\/td>\n<\/tr>\n
398<\/td>\nC.3.9.2 iTake and iRelease commands <\/td>\n<\/tr>\n
399<\/td>\nSyntax
Rules
Example <\/td>\n<\/tr>\n
400<\/td>\nC.3.10 Miscellaneous commands
C.3.10.1 iNote command
Syntax
Recommendations
Example A <\/td>\n<\/tr>\n
401<\/td>\nExample B
C.3.10.2 iSetFail command
Syntax
Rules
Recommendations
Examples
C.3.11 Low-level commands <\/td>\n<\/tr>\n
402<\/td>\nC.3.11.1 iTMSreset and iTRST commands
Syntax
Rules <\/td>\n<\/tr>\n
403<\/td>\nRecommendations
Example
C.3.11.2 iTMSidle command
Syntax
Rules
Examples <\/td>\n<\/tr>\n
404<\/td>\nC.4 PDL Level 1 command reference <\/td>\n<\/tr>\n
405<\/td>\nC.4.1 Level-1 PDL operation
C.4.2 iGet command <\/td>\n<\/tr>\n
406<\/td>\nSyntax
Rules <\/td>\n<\/tr>\n
407<\/td>\nExample A
Example B <\/td>\n<\/tr>\n
408<\/td>\nExample C
Example D
Example E <\/td>\n<\/tr>\n
409<\/td>\nExample F
Example G <\/td>\n<\/tr>\n
410<\/td>\nC.4.3 iGetStatus command
Syntax
Rules
Example
C.5 Example BSDL and PDL for the use model <\/td>\n<\/tr>\n
411<\/td>\nC.5.1 BSDL Packages for IP
MEMB <\/td>\n<\/tr>\n
412<\/td>\nSERDES
C.5.2 BSDL files for components
Chip_A <\/td>\n<\/tr>\n
413<\/td>\nChip_B <\/td>\n<\/tr>\n
414<\/td>\nChip_C <\/td>\n<\/tr>\n
415<\/td>\nC.5.3 PDL files supplied by IP supplier
MEMB
SERDES <\/td>\n<\/tr>\n
416<\/td>\nC.5.4 PDL files supplied by component supplier
Chip_A <\/td>\n<\/tr>\n
417<\/td>\nChip_B
Chip_C
C.5.5 PDL files coded by test engineer
U1
U2 <\/td>\n<\/tr>\n
418<\/td>\nU3
U4
UUT <\/td>\n<\/tr>\n
420<\/td>\nAnnex D (informative) Integrated examples of BSDL and PDL
D.1 Initialization example structure and procedures
D.1.1 Initialization example using register description attributes <\/td>\n<\/tr>\n
427<\/td>\nD.1.2 Example PDL for INIT example <\/td>\n<\/tr>\n
430<\/td>\nD.2 Multiple wrapper serial port structure and procedures
D.2.1 Wrapper serial port structural description
Single WSP <\/td>\n<\/tr>\n
432<\/td>\nMultiple selectable and gated WSP <\/td>\n<\/tr>\n
439<\/td>\nD.2.2 Wrapper serial port example
Reg_1500.pdl
Reg_1500S.pdl
Reg_1500_Assm.pdl <\/td>\n<\/tr>\n
442<\/td>\nAnnex E (informative)
\nExample iApply execution flow <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Test Access Port and Boundary-Scan Architecture (Redline)<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2013<\/td>\n444<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":457003,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-456996","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/456996","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/457003"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=456996"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=456996"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=456996"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}