{"id":79712,"date":"2024-10-17T18:37:10","date_gmt":"2024-10-17T18:37:10","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1076-4-1996\/"},"modified":"2024-10-24T19:41:03","modified_gmt":"2024-10-24T19:41:03","slug":"ieee-1076-4-1996","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1076-4-1996\/","title":{"rendered":"IEEE 1076.4 1996"},"content":{"rendered":"

New IEEE Standard – Inactive – Superseded. Superseded by 1076.4-2000. The VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined. It creates a methodology that promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL. You will receive an email from Customer Service with the URL needed to access this publication online.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nTitle Page <\/td>\n<\/tr>\n
3<\/td>\nIntroduction <\/td>\n<\/tr>\n
4<\/td>\nParticipants <\/td>\n<\/tr>\n
8<\/td>\nCONTENTS <\/td>\n<\/tr>\n
11<\/td>\n1. Overview
1.1 Intent and scope of this standard
1.2 Structure and terminology of this standard
1.3 Syntactic description <\/td>\n<\/tr>\n
13<\/td>\n1.4 Semantic description
1.5 Front matter, examples, figures, notes, and annexes <\/td>\n<\/tr>\n
14<\/td>\n2. References <\/td>\n<\/tr>\n
15<\/td>\n3. Basic elements of the VITAL ASIC modeling
3.1 VITAL modeling levels and compliance <\/td>\n<\/tr>\n
16<\/td>\n3.2 VITAL standard packages
3.3 VITAL specification for timing data insertion <\/td>\n<\/tr>\n
18<\/td>\n4. The VITAL Level 0 specification
4.1 The VITAL_Level0 attribute
4.2 General usage rules <\/td>\n<\/tr>\n
19<\/td>\n4.3 The VITAL Level 0 entity interface <\/td>\n<\/tr>\n
27<\/td>\n4.4 The VITAL Level 0 architecture body <\/td>\n<\/tr>\n
29<\/td>\n5. Backannotation
5.1 Backannotation methods <\/td>\n<\/tr>\n
30<\/td>\n5.2 The VITAL SDF map <\/td>\n<\/tr>\n
43<\/td>\n6. The VITAL Level 1 specification
6.1 The VITAL_Level1 attribute
6.2 The VITAL Level 1 architecture body <\/td>\n<\/tr>\n
44<\/td>\n6.3 The VITAL Level 1 architecture declarative part
6.4 The VITAL Level 1 architecture statement part <\/td>\n<\/tr>\n
53<\/td>\n7. Predefined primitives and tables
7.1 VITAL logic primitives <\/td>\n<\/tr>\n
55<\/td>\n7.2 VitalResolve
7.3 VITAL table primitives <\/td>\n<\/tr>\n
61<\/td>\n8. Timing constraints
8.1 Timing check procedures <\/td>\n<\/tr>\n
63<\/td>\n8.2 Modeling negative timing constraints <\/td>\n<\/tr>\n
69<\/td>\n9. Delay selection
9.1 VITAL delay types and subtypes <\/td>\n<\/tr>\n
70<\/td>\n9.2 Transition-dependent delay selection
9.3 Glitch handling <\/td>\n<\/tr>\n
71<\/td>\n9.4 Path delay procedures <\/td>\n<\/tr>\n
73<\/td>\n9.5 Delay selection in VITAL primitives
9.6 VitalExtendToFillDelay <\/td>\n<\/tr>\n
75<\/td>\n10. The VITAL standard packages <\/td>\n<\/tr>\n
76<\/td>\nAnnex A\u2014Syntax summary <\/td>\n<\/tr>\n
80<\/td>\nAnnex B\u2014Glossary <\/td>\n<\/tr>\n
81<\/td>\nAnnex C\u2014Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard VITAL Application-Specific Integrated Circuit (ASIC) Modeling Specification<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n1996<\/td>\n81<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":79713,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-79712","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/79712","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/79713"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=79712"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=79712"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=79712"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}