BS IEC 62548-1:2023 – TC:2024 Edition
$280.87
Tracked Changes. Photovoltaic (PV) arrays – Design requirements
| Published By | Publication Date | Number of Pages |
| BSI | 2024 | 243 |
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 137 | undefined |
| 139 | CONTENTS |
| 143 | FOREWORD |
| 145 | 1 Scope 2 Normative references |
| 148 | 3 Terms, definitions, symbols and abbreviated terms 3.1 Terms and definitions |
| 154 | 3.2 Symbols |
| 157 | 3.3 Abbreviated terms 4 Compliance with IEC 60364 series |
| 158 | 5 PV array system configuration 5.1 General 5.1.1 Functional configuration of a PV system 5.1.2 PV system topologies Figures Figure 1 – General functional configuration of a PV powered system |
| 159 | 5.1.3 Array electrical diagrams |
| 160 | Figure 2 – PV array diagram – single string example |
| 161 | Figure 3 – PV array diagram – multiple parallel string example |
| 162 | Figure 4 – PV array diagram – multiple parallel string examplewith array divided into sub-arrays |
| 163 | Figure 5 – PV array example using a PCE with multiple MPPT DC inputs |
| 164 | Figure 6 – PV array example using a PCE with multiple DCinputs internally connected to a common DC bus |
| 165 | 5.1.4 Use of PCE with multiple DC inputs 5.1.5 PV arrays using DCUs |
| 166 | Figure 7 – PV string constructed using DCUs |
| 167 | Figure 8 – Example of partial DCU string |
| 168 | Figure 9 – PV parallel strings constructed using DCUs |
| 169 | Figure 10 – PV string(s) connected to DCUs |
| 170 | 5.1.6 Series-parallel configuration 5.1.7 Batteries in systems |
| 171 | 5.1.8 Backfeed and reverse currents 5.1.9 Considerations due to prospective fault current conditions within a PV array 5.1.10 Considerations due to operating temperature |
| 172 | 5.1.11 Performance issues |
| 173 | 5.1.12 Potential induced degradation 5.1.13 Corrosion 5.1.14 Mechanical design |
| 174 | 5.1.15 Mechanical loads on PV structures |
| 176 | 6 Safety issues 6.1 General 6.2 Protection against electric shock 6.2.1 General 6.2.2 Protective measure: double or reinforced insulation 6.2.3 Protective measure: extra-low-voltage provided by SELV or PELV 6.3 Protection against thermal effects 6.3.1 General |
| 177 | 6.3.2 Protection against fire caused by arcs 6.3.3 Protection against arc flash 6.4 Protection against the effects of insulation faults 6.4.1 General |
| 178 | 6.4.2 Segregation of PV circuits from other circuits 6.4.3 Earth fault detection and indication requirements |
| 180 | Tables Table 1 – Requirements for different system types basedon PCE separation and PV array functional earthing |
| 181 | Table 2 – Minimum insulation resistance thresholds for detection of failure of insulation to earth |
| 183 | Table 3 – Trip current of functional earthing overcurrent protection. |
| 184 | 6.5 Protection against overcurrent 6.5.1 General 6.5.2 Requirement for overcurrent protection |
| 185 | 6.5.3 Requirements for overcurrent protection of circuits |
| 186 | Table 4 – Overcurrent protection nominal rating |
| 187 | 6.5.4 Overcurrent protection for PV systems connected to batteries Figure 11 – Example of a PV array diagram where strings are groupedunder one overcurrent protection device per group |
| 188 | 6.5.5 Overcurrent protection location 6.6 Protection against effects of lightning and overvoltage 6.6.1 General |
| 189 | 6.6.2 Protection against overvoltage Table 5 – Calculation of the critical length Lcrit |
| 190 | 7 Selection and erection of electrical equipment 7.1 General |
| 191 | 7.2 Component requirements 7.2.1 General 7.2.2 Current rating of PV circuits |
| 192 | 7.2.3 PV modules Table 6 – Minimum current rating of circuits |
| 193 | 7.2.4 PV array and PV string combiner boxes |
| 194 | 7.2.5 Fuses 7.2.6 Circuit breakers used for overcurrent protection |
| 195 | 7.2.7 Isolation means and isolation means with breaking capabilities |
| 197 | 7.2.8 Cables |
| 199 | 7.2.9 Plugs, sockets and connectors in PV circuits Figure 12 – Examples of reinforced protection of wiring |
| 200 | 7.2.10 Wiring in combiner boxes 7.2.11 Bypass diodes |
| 201 | 7.2.12 Blocking diodes 7.2.13 Power conversion equipment (PCE) including DC conditioning units (DCUs) |
| 202 | 7.3 Location and installation requirements 7.3.1 Isolation means Table 7 – Isolation means in PV array installations |
| 204 | 7.3.2 Earthing and bonding arrangements |
| 205 | Figure 13 – PV array exposed conductive partsfunctional earthing/bonding decision tree |
| 206 | Figure 14 – Exposed conductive parts earthing in a PV array |
| 207 | 7.3.3 Wiring system |
| 210 | Figure 15 – Examples of string wiring with minimum loop area |
| 211 | 8 Acceptance 9 Operation/maintenance 10 Marking and documentation 10.1 Equipment marking 10.2 Requirements for signs 10.3 Identification of a PV installation 10.4 Labelling of PV array and PV string combiner boxes |
| 212 | 10.5 Labelling of isolation means 10.5.1 General 10.5.2 PV array isolation means with breaking capabilities 10.6 Warning sign for anti-PID equipment 10.7 Documentation |
| 213 | Annex A (informative)Examples of signs Figure A.1 – Example of sign required on PV array combiner boxes (10.4) Figure A.2 – Example of switchboard sign for identification of PV on a building |
| 214 | Annex B (informative)Examples of system earthingconfigurations in PV arrays Figure B.1 – Functionally earthed system topologies |
| 215 | Figure B.2 – Non-earth-referenced system topologies |
| 216 | Figure B.3 – Non-separated system topologies |
| 217 | Annex C (informative)Blocking diode C.1 General C.2 Use of blocking diodes to prevent overcurrent/fault current in arrays C.3 Examples of blocking diode use in fault situations C.3.1 General C.3.2 Short circuit in PV string |
| 218 | Figure C.1 – Effect of blocking diode where there is a short circuit in PV string Figure C.2 – Effect of blocking diode where there is an earth faulton a system with earthing on the negative side |
| 219 | C.4 Specification of blocking diode C.5 Heat dissipation design for blocking diode Figure C.3 – Effect of blocking diode where there isan earth fault on a system with positive side earthing |
| 221 | Annex D (informative)Arc fault detection and interruption in PV arrays Figure D.1 – Examples of types of arcs in PV arrays |
| 222 | Annex E (normative)DVC limits Table E.1 – Summary of the limits of the decisive voltage classes |
| 223 | Annex F (normative)Determination of maximum voltage and maximum currents in PV circuits F.1 UOC MAX F.1.1 PV array maximum voltage |
| 224 | F.1.2 PV strings constructed using DC conditioning units Table F.1 – Voltage correction factors for crystallineand multi-crystalline silicon PV modules |
| 225 | F.2 String maximum current F.3 Calculation of potential fault currents originating from the array F.3.1 General F.3.2 String F.3.3 Sub-array F.3.4 Array |
| 226 | F.4 KI factor – general F.5 KCorr factor – under unique environmental conditions Table F.2 – Environmental conditions covered by KCorr = 1,0 |
| 227 | F.6 KCorr factor – non optimally oriented monofacial arrays F.7 KCorr factor – bifacial arrays Table F.3 – Example KCorr values at different orientations and tilt for 47º north latitude |
| 228 | F.8 KCorr factor – for arrays containing non-optimally oriented bifacial modules |
| 229 | Annex G (normative)Backfeed current and PV reverse currents under fault conditions G.1 General G.2 Illustrated examples Figure G.1 – Backfeed from inverter with single PV input and internal battery |
| 230 | Figure G.2 – Inverter with multiple PV inputs and external battery |
| 231 | G.3 Backfeed currents and PV reverse currents where subarrays are not combined in the PCE Figure G.3 – Backfeed where subarrays are combined externally to PCE |
| 233 | Annex H (normative)Anti-PID H.1 General H.2 DC bias applied during night Figure H.1 – Example anti-PID control using bias on dc side at night |
| 234 | H.3 DC bias applied to array output Figure H.2 – Example of anti-PID control using bias on DC side |
| 235 | H.4 DC bias applied to AC system Figure H.3 – Example of anti-PID control using bias on AC side |
| 237 | Annex I (informative)Arc flash |
| 238 | Annex J (normative)Qualification of DCU group voltage J.1 Overview J.2 Test 1: Maximum voltage operational test procedure J.3 Test 2: Overvoltage test |
| 240 | Bibliography |
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