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BS ISO 17458-4:2013

BS ISO 17458-4:2013

$215.11

Road vehicles. FlexRay communications system – Electrical physical layer specification

Published By Publication Date Number of Pages
BSI 2013 214
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PDF Catalog

PDF Pages PDF Title
11 1 Scope
2 Normative references
3 Terms, definitions, symbols and abbreviated terms
3.1 Terms and definitions
20 3.2 Abbreviated terms
22 3.3 Symbols
23 4 Document reference according to OSI model
24 5 Conventions
5.1 General
5.2 Notational and parameter prefix conventions
25 5.3 Important preliminary notes
5.3.1 Bus speed
5.3.2 Conformance tests
5.3.3 Conformance test of FlexRay communication controllers
26 6 Communication channel basics
6.1 Objective
6.2 Propagation delay
27 6.2.1 Asymmetric delay
28 6.3 Frame TSS length change
6.4 Symbol length change
29 6.5 FES1 length change
6.6 Collisions
30 6.7 Stochastic jitter
6.7.1 Introduction
6.7.2 Stochastic jitter on data edges
6.7.3 Stochastic jitter on TSS length change
6.7.4 Stochastic jitter on symbol length change
6.8 Wakeup patterns
6.8.1 Overview
6.8.2 Standard wakeup pattern
31 6.8.3 Alternative wakeup patterns
32 7 Principle of FlexRay networking
7.1 Objective
7.2 Interconnection of nodes
33 7.3 Electrical signalling
7.3.1 Overview
34 7.3.2 Bus state: Idle
7.3.3 Bus state: Data_1
7.3.4 Bus state: Data_0
8 Network components
8.1 Objective
8.2 Cables
35 8.3 Connectors
8.4 Cable termination
8.4.1 Terminated cable end
36 8.4.2 Un-terminated cable end
37 8.5 Termination concept
8.6 Common mode chokes
8.7 DC bus load
38 9 Network topology
9.1 Objective
39 9.2 Point-to-point connection
9.3 Passive star
40 9.4 Linear passive bus
41 9.5 Active star network
42 9.6 Cascaded active stars
9.7 Hybrid topologies
43 9.8 Dual channel topologies
10 Asymmetric delay budget
10.1 Objective
44 10.2 Basic topology for asymmetric delay budget
10.3 Definition of Test Planes
46 10.4 Requirements to the asymmetric delay budget
10.5 Definition of maximum asymmetric delay portions
53 10.6 Other networks
11 Signal integrity
11.1 Objective
54 11.2 Mask test at TP1 / TP11
11.2.1 Overview
55 11.2.2 Standard TP1 Mask
11.2.3 TP1 mask for functional class “Bus driver increased voltage amplitude transmitter”
57 11.2.4 Standard TP11 Mask
11.2.5 TP11 mask for functional class “Active star increased voltage amplitude transmitter”
59 12 Electrical bus driver
12.1 Overview
60 12.2 Operation modes
12.2.1 General
12.2.2 BD_Normal mode
12.2.3 BD_Standby mode
12.2.4 BD_Sleep mode (optional)
12.2.5 BD_ReceiveOnly mode (optional)
61 12.2.6 BD_Off
12.3 Operation mode transitions
12.3.1 Overview
63 12.3.2 Mode transitions due to detection of undervoltage conditions
12.3.3 Mode transitions in case of undervoltage recovery
12.3.4 Mode transitions due to detected wakeup events
12.3.5 Power on event
12.3.6 Power off event
12.4 Bus driver – communication controller interface
12.4.1 General
64 12.4.2 RxD – behaviour
12.4.3 TxD/TxEN behaviour in case a bus driver – bus guardian interface is implemented
65 12.4.4 TxD/TxEN – behaviour in case a bus driver – bus guardian interface is not implemented
12.4.5 TxEN – RxD loopback
66 12.4.6 Electrical characteristics
12.4.6.1 RxD
12.4.6.2 TxD
67 12.5 Bus driver – bus guardian interface (optional)
12.6 Bus driver – host interface
12.6.1 Overview
12.6.2 Hard wired signals (Option A)
12.6.2.1 Operation mode control
68 12.6.2.2 Signalling on ERRN
12.6.2.2.1 Overview
69 12.6.2.2.2 Signalling on ERRN, when only STBN control input available
70 12.6.2.2.3 Signalling on ERRN, when STBN and EN are available
71 12.6.3 Serial peripheral interface (SPI) (Option B)
12.7 Bus driver – power supply interface
12.7.1 Overview
72 12.7.2 VCC supply voltage monitoring
12.7.3 VBAT supply voltage monitoring
12.7.4 Inhibit output (optional)
73 12.8 Bus driver – level shift interface (optional)
12.8.1 Overview
12.8.2 VIO voltage monitoring
12.9 Bus driver – bus interface
12.9.1 Overview
74 12.9.2 Transmitter characteristics
76 12.9.3 Transmitter behaviour at transition from idle to active and vice versa
77 12.9.4 Receiver behaviour (in non-low power mode)
79 12.9.5 Receiver characteristics
81 12.9.6 Receiver timing characteristics
84 12.9.7 Receiver behaviour at transition from idle to active and vice versa
85 12.9.8 Receiver behaviour (in low power mode)
86 12.9.9 Bus driver – bus interface behaviour, when in BD_Off mode
12.9.10 Bus driver – bus interface behaviour under short-circuit conditions
12.9.11 Bus driver – bus interface simulation model parameters
87 12.10 Bus driver – wakeup interface (optional)
12.10.1 General
12.10.2 Wakeup via dedicated WAKE pin
12.10.3 Local wakeup operating requirements
88 12.11 Remote wakeup event detector (optional)
12.11.1 Wakeup with wakeup patterns independent of data rate
12.11.2 Wakeup with frames in 10 Mbit/s systems
12.11.3 Wakeup state machine
89 12.11.4 Remote wakeup operating requirements
90 12.12 Bus driver behaviour under fault conditions
12.12.1 Environmental errors
92 12.12.2 Behaviour of unconnected digital input signals
93 12.12.3 Behaviour with dynamic low battery voltage
12.12.4 Behaviour with dynamic low supply voltage
94 12.12.5 Bus failure detection
95 12.12.6 Over-temperature protection
12.13 Bus driver functional classes
12.13.1 Overview
12.13.2 Functional class “Bus driver voltage regulator control”
12.13.3 Functional class “Bus driver – bus guardian interface”
12.13.4 Functional class “Bus driver internal voltage regulator”
96 12.13.5 Functional class “Bus driver logic level adaptation”
12.13.6 Functional class “Bus driver remote wakeup”
12.13.7 Functional class “Bus driver increased voltage amplitude transmitter”
97 12.14 Bus driver signal summary
98 13 Active Star
13.1 Overview
13.2 Hardware overview
13.2.1 Overview
100 13.2.2 Communication paths
13.3 Signal timing
13.3.1 Objective
101 13.3.2 Signal timing – frames
103 13.3.3 Signal timing – system view
13.3.4 Signal timing – symbols
105 13.3.5 Signal timing – collisions
107 13.3.6 Signal timing – wakeup patterns
108 13.4 Active star device operation modes
13.4.1 Introduction
109 13.4.2 AS_Sleep
110 13.4.3 AS_Normal
13.4.4 AS_Standby
13.4.5 AS_Off
13.5 Autonomous power moding flag (APM flag)
111 13.6 Branch operating states
13.6.1 Introduction
112 13.6.2 Branch_Off
13.6.3 Branch_LowPower
113 13.6.4 Branch_Idle
13.6.5 Branch_Transmit
13.6.6 Branch_Receive
13.6.7 Branch_Disabled
114 13.6.8 Branch_FailSilent
13.6.9 Branch_TxOnly
13.7 Branch transmitter and receiver circuit
13.7.1 Receiver characteristics
13.7.2 Receiver behaviour (in non-low power modes)
13.7.3 Receiver behaviour (in low power modes)
13.7.4 Receiver behaviour (in AS_Off mode)
13.7.5 Active Star – bus interface simulation model parameters
115 13.7.6 Transmitter characteristics
13.8 Active star – communication controller interface (optional)
13.8.1 Overview
116 13.8.2 Transmitter timing characteristics
118 13.8.3 Transmitter behaviour at transition from idle to active and vice versa
120 13.8.4 Receiver behaviour at transition from idle to active and vice versa
122 13.8.5 Receiver timing characteristics
123 13.8.6 TxEN – RxD loopback
124 13.8.7 Electrical behaviour
13.8.7.1 RxD
13.8.7.2 TxD
125 13.9 Active star – bus guardian interface (optional)
13.10 Active star – host interface (optional)
13.11 Active star – power supply interface
13.11.1 Introduction
126 13.11.2 Inhibit output (optional)
127 13.11.3 VCC supply voltage monitoring (optional)
13.11.4 VBAT supply voltage monitoring
13.11.5 Supply voltage monitoring
128 13.12 Active star – level shift interface (optional)
13.12.1 Overview
13.12.2 VIO voltage monitoring
13.13 Active star – bus interface
129 13.14 Active star – wake interface (optional)
13.15 Active star functional classes
13.15.1 Functional class: “Active star – communication controller interface”
13.15.2 Functional class: “Active star – bus guardian interface”
13.15.3 Functional class “Active star – voltage regulator control”
13.15.4 Functional class “Active star – internal voltage regulator”
13.15.5 Functional class “Active star – logic level adaptation”
13.15.6 Functional class “Active star – host interface”
130 13.15.7 Functional class “Active star increased voltage amplitude transmitter”
13.16 Active star behaviour under fault conditions
13.16.1 Environmental faults
131 13.16.2 Behaviour of unconnected digital input signals
13.16.3 Behaviour with dynamic low battery voltage
13.16.4 Behaviour with dynamic low supply voltage
132 13.16.5 Over-temperature protection
13.17 Active star signal summary
133 14 Interface definitions
14.1 Overview
14.2 Communication controller – bus driver interface
14.2.1 Introduction
14.2.2 TxEN
14.2.3 TxD
135 14.2.4 RxD
14.2.5 Receiver asymmetry
136 14.2.6 Communication controller system timing
14.3 Host
137 15 General features for FlexRay physical layer parts
15.1 Objective
15.2 Voltage limits for digital output signals
15.3 Input voltage thresholds for digital signals
138 15.4 ESD protection on chip level (HBM)
15.5 ESD protection on chip level (IEC61000-4-2)
15.6 ESD protection on ECU level
15.7 Operating temperature
139 15.8 Serial peripheral interface (SPI)
15.8.1 SPI definition
140 15.8.2 Behaviour of unconnected SPI input pins
211 Blank Page
212 Blank Page
BS ISO 17458-4:2013
$215.11